1. Field of the Invention
This invention relates to a means for controlling access by a plurality of processor units and input/output devices to local memories associated with the processor units, and to a system memory over a system bus; and, more particularly, to a bus arbitration system and method for use in a data processing system which operates on clocked cycles to grant a request by processor units and input/output device to access an associated local memory or a system memory over a system bus and, where possible, to permit a processor unit to access its associated local memory over a local bus in parallel to a selected one of processor units and the input/output devices utilizing the system bus for accessing memories.
2. Description of the Prior Art
It is known in the art for a data processing system to have a plurality of processor units, each of which has its own associated local memory, and to have shared access over the data processing system's system bus to a global or system memory. Also, it is known in the art for input/output devices to access, over the system bus, both the system memory and associated local memories.
In the event that one or more processors or the input/output devices require accessing either the system memory or one of the associated local memories, a conflict is present as to which requesting unit is to be given the right to utilize the system bus. When a plurality of processors and input/output devices require use of shared resources for performance, and only a single unit can be granted access to the system bus during a clock cycle, system degradation results in terms of decreased operating speeds due to the inability of more than one unit to utilize the system bus for accessing memories.
The prior art data processing systems tolerate such conflicts in shared resources in that the data processing system has some economics from being able to share input/output devices, power supplies, cabinets, and the like, among various processor units and input/output devices. However, if system performance levels are to be increased, it is necessary to increase the bandwidth of the system bus or to provide for additional parallel accessing paths without seriously affecting the economics of the data processing system in terms of the price/performance ratio.